1. Field of the Invention
This invention relates to an apparatus and a method for generating an output clock signal, particularly relates to an apparatus and a method for generating an output clock signal using an internal clock signal.
2. Description of the Prior Art
A Serial interface, such as an I2C interface, PCI Express, and Universal Serial Bus (USB), is a common interface for data transmission. The I2C interface comprises a data line and a clock line. The USB interface comprises two data lines, Data+ and Data−, and two power lines, Vdd and Gnd. These two data lines Data+ and Data− are differential signals.
Please refer to FIG. 1A; FIG. 1A shows a block diagram of the structure of a serial data communication using the serial interface. Please refer to FIG. 1A. The structure of the serial signal communication comprises a master device 110 and a slayer device 120. The master device 110 and the slayer device 120 are reference to a reference clock. The reference clock can be provided by a precise crystal oscillator 150 or be generated by an external crystal oscillator 130 and input into an internal phase-lock loop (PLL) 140. Conventionally, because frequency errors of the reference clocks could not be avoided, the reference clocks of the conventional master device 110 and the conventional slayer device 120 could not be exactly the same and synchronized. In the I2C interface, the I2C interface includes the clock link for transferring the reference clock from the master device 110 to the slave device 120 such that the master device 110 and the slave device 120 can be synchronization. In a USB, the USB signal contains a data signal and a synchronization signal such that the master device and the slave device can be synchronization according to the synchronization signal.
FIG. 1B shows the waveform of a USB signal. The USB signal 160 comprises a synchronization signal 170 and a data signal 180. When the USB receiver, such as the slayer device 120, receives the synchronization signal 170, the USB receiver compensates the sampling frequency of the received data signal 180 to avoid errors. In I2C, the I2C receiver uses the clock signal of the clock line as a reference to determine the sampling frequency of the data signal of the data line.
The conventional serial interface requires an external crystal oscillator. In additions, the reference clock frequencies of the conventional master device 110 and the slayer device 120 are not exactly the same.
Therefore, this invention provides a method and apparatus to generate a clock signal, wherein an external crystal oscillator is not required and the frequency of the clock signal is substantially the same as the frequency of the clock signal generated by a remote serial transmitting device.
Shinmori (U.S. Pat. No. 6,107,846) discloses a frequency multiplication circuit which is able to generate an output signal having a frequency obtained by multiplying an input external clock signal (see lines 1˜3 of ABSTRACT of Shinmori). The frequency of the output signal is multiple times of that of the input external clock signal, and therefore the period of the output signal definitely is NOT the same as the period of the input external clock signal. Moreover, from the FIGS. 2, 4, 6 and 8 of Shinmori (not shown here), it can be seen that the output signal CLK2 contains uneven duty cycles due to the fact that, the reference clock signal CLK0 is output as the output signal CLK2 only when the output terminal Q2 is at an active level, and a low signal will be output as the output signal CLK2 when the output terminal Q2 is at an inactive level. Therefore, part of the duty cycles of the output signal CLK2 are equal to the duty cycles of reference clock signal CLK0, but some others are not. That is, the frequency multiplication circuit disclosed by Shinmori is merely a frequency multiplying circuit that is capable of generating an output signal having a frequency that is N-times as high as the input external clock signal. However, Shinmori does not disclose, teach nor suggest an apparatus to generate a clock signal as which disclosed in the present invention that, wherein the external crystal oscillator is not required and the frequency and duty cycle of the input clock signal is substantially the same as the frequency and duty cycle of the output clock signal generated by the apparatus.